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TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
Rev. 01 -- 5 March 2008 Product data sheet
1. General description
The TDF8591TH is a high-efficiency class-D audio power amplifier with low power dissipation for application in car audio systems. The typical output power is 2 x 100 W into 4 . The TDF8591TH is available in an HSOP24 power package with a small internal heat sink. Depending on the supply voltage and load conditions, a small or even no external heat sink is required. The amplifier operates over a wide supply voltage range from 14 V to 29 V and consumes a low quiescent current.
2. Features
I I I I I I I I I I I I I I I Zero dead time switching Advanced output current protection No DC offset induced pop noise at mode transitions High efficiency Supply voltage from 14 V to 29 V Low quiescent current Usable as a stereo Single-Ended (SE) amplifier or as a mono amplifier in Bridge-Tied Load (BTL) Fixed gain of 26 dB in SE and 32 dB in BTL High BTL output power: 310 W into 4 Suitable for speakers in the 2 to 8 range High supply voltage ripple rejection Internal oscillator or synchronized to an external clock Full short-circuit proof outputs across load and to supply lines Thermal foldback and thermal protection AEC-Q100 qualified
3. Ordering information
Table 1. Ordering information Package Name TDF8591TH HSOP24 Description plastic, heatsink small outline package; 24 leads; low stand-off height Version SOT566-3 Type number
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
4. Block diagram
VDDA2 3 VDDA1 10 STABI DIAG 18 13 VDDP2 23 VDDP1 14 15 IN1M IN1P 9 8 INPUT STAGE PWM MODULATOR RELEASE1 SWITCH1 ENABLE1 SGND1 OSC MODE 11 7 6 OSCILLATOR MODE MANAGER TEMPERATURE SENSOR CURRENT PROTECTION VOLTAGE PROTECTION mute STABI CONTROL AND HANDSHAKE DRIVER HIGH BOOT1
16
OUT1
DRIVER LOW VSSP1
TDF8591TH
VDDP2 22 BOOT2
SGND2
2 mute ENABLE2 SWITCH2 INPUT STAGE PWM MODULATOR RELEASE2 CONTROL AND HANDSHAKE DRIVER HIGH 21
IN2P IN2M
5 4
OUT2
DRIVER LOW 17 VSSP1 20 VSSP2
001aah194
1 VSSA2
12 VSSA1
24 VSSD
19 n.c.
Fig 1. Block diagram
5. Pinning information
5.1 Pinning
VSSD 24 VDDP2 23 BOOT2 22 OUT2 21 VSSP2 20 n.c. 19 STABI 18 VSSP1 17 OUT1 16 BOOT1 15 VDDP1 14 DIAG 13
001aah195
1 2 3 4 5
VSSA2 SGND2 VDDA2 IN2M IN2P MODE OSC IN1P IN1M
TDF8591TH
6 7 8 9
10 VDDA1 11 SGND1 12 VSSA1
Fig 2. Pin configuration (top view)
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
2 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
5.2 Pin description
Table 2. Symbol VSSA2 SGND2 VDDA2 IN2M IN2P MODE OSC IN1P IN1M VDDA1 SGND1 VSSA1 DIAG VDDP1 BOOT1 OUT1 VSSP1 STABI n.c. VSSP2 OUT2 BOOT2 VDDP2 VSSD
[1]
Pin description Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Description negative analog supply voltage for channel 2 signal ground for channel 2 positive analog supply voltage for channel 2 negative audio input for channel 2 positive audio input for channel 2 mode selection input: standby, mute or operating oscillator frequency adjustment or tracking input positive audio input for channel 1 negative audio input for channel 1 positive analog supply voltage for channel 1 signal ground for channel 1 negative analog supply voltage for channel 1 diagnostic for activated current protection positive power supply voltage for channel 1 bootstrap capacitor for channel 1 PWM output from channel 1 negative power supply voltage for channel 1 decoupling of internal stabilizer for logic supply not connected negative power supply voltage for channel 2 PWM output from channel 2 bootstrap capacitor for channel 2 positive power supply voltage for channel 2 negative digital supply voltage[1]
The heatsink is internally connected to VSSD.
6. Functional description
6.1 Introduction
The TDF8591TH is a dual channel audio power amplifier using class-D technology. The audio input signal is converted into a Pulse Width Modulated (PWM) signal via an analog input stage and PWM modulator. To enable the output power transistors to be driven, this digital PWM signal is applied to a control and handshake block and driver circuits for both the high-side and low-side. An external 2nd-order low-pass filter converts the PWM output signal to an analog audio signal across the loudspeakers.
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
3 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
The TDF8591TH contains two independent amplifier channels with a differential input stage, high output power, high efficiency (90 %), low distortion and a low quiescent current. The amplifier channels can be connected in the following configurations:
* Mono Bridge-Tied Load (BTL) amplifier * Dual Single-Ended (SE) amplifiers
The TDF8591TH also contains circuits common to both channels such as the oscillator, all reference sources, the mode functionality and a digital timing manager. For protection a thermal foldback, temperature, current and voltage protection are built in.
6.2 Mode selection
The TDF8591TH can be switched in three operating modes via pin MODE:
* Standby mode; the amplifiers are switched off to achieve a very low supply current * Mute mode; the amplifiers are switching idle (50 % duty cycle), but the audio signal at
the output is suppressed by disabling the VI-converter input stages
* Operating mode; the amplifiers are fully operational with output signal
The input stage (see Figure 1) contributes to the DC offset measured at the amplifier output. To avoid pop noise the DC output offset voltage should be increased gradually at a mode transition from mute to operating, or vice versa, by limiting the dVMODE/dt on pin MODE, resulting in a small dVO(offset)/dt for the DC output offset voltage. The required time constant for a gradually increase of the DC output offset voltage between mute and operating is generated via an RC network on pin MODE. An example of a switching circuit for driving pin MODE is illustrated in Figure 3 and explained in Table 3.
VDDP
5.6 k 5.6 k
MODE
5.6 k 5.6 V S1 S2 100 F (10 V)
SGND
001aad836
Fig 3. Example of mode selection circuit Table 3. S1 closed closed open open Mode selection S2 closed open closed open Mode selection Standby mode Standby mode Mute mode Operating mode
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
4 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
The value of the RC time constant should be dimensioned for 500 ms. If the 100 F capacitor is left out of the application the voltage on pin MODE will be applied with a much smaller time constant, which might result in audible pop noises during start-up (depending on DC output offset voltage and used loudspeaker). In order to fully charge the coupling capacitors at the inputs, the amplifier will remain automatically in Mute mode for approximately 150 ms before switching to Operating mode. A complete overview of the start-up timing is given in Figure 4.
audio
switching
VMODE operating
5V
2.5 V
mute
0 V (SGND)
standby 100 ms >50 ms time
audio
switching
VMODE operating
5V
0 V (SGND)
standby 100 ms 50 ms time
001aad837
Fig 4. Timing on mode selection input
6.3 Pulse width modulation frequency
The output signal of the amplifier is a PWM signal with a switching frequency that is set by an external resistor Rext(OSC) connected between pins OSC and VSSA. An optimum setting for the carrier frequency is between 300 kHz and 350 kHz. An external resistor Rext(OSC) of 30 k sets the frequency to 310 kHz.
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
5 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
If two or more class-D amplifiers are used in the same audio application, it is recommended to synchronize the switching frequency of all devices to an external clock (see Section 12.3).
6.4 Protections
The following protections are included in TDF8591TH:
* * * * *
Thermal Foldback (TF) OverTemperature Protection (OTP) OverCurrent Protection (OCP) Window Protection (WP) Supply voltage protections - UnderVoltage Protection (UVP) - OverVoltage Protection (OVP) - Unbalance Protection (UBP)
The reaction of the device on the different fault conditions differs per protection and is described in Section 6.4.1 to Section 6.4.5.
6.4.1 Thermal foldback
If the junction temperature Tj > 145 C, then the TF gradually reduced the gain, resulting in a smaller output signal and less dissipation. At Tj = 155 C the outputs are fully muted.
6.4.2 Overtemperature protection
If Tj > 160 C, then the OTP will shut down the power stage immediately.
6.4.3 Overcurrent protection
The OCP will detect a short-circuit between the loudspeaker terminals or if one of the loudspeaker terminals is short-circuited to one of the supply lines. If the output current tends to exceed the maximum output current of 12 A, the output voltage of the TDF8591TH will be regulated to a level where the maximum output current is limited to 12 A while the amplifier outputs remain switching, the amplifier does not shut down. When this active current limiting continues longer than a time (see Figure 5) the capacitor on pin DIAG is discharged below a threshold value and the TDF8591TH shuts down. Activation of current limiting and the triggering of the OCP is observed at pin DIAG (see Figure 5). A maximum value for the capacitor on pin DIAG is 47 pF. The reference voltage on pin DIAG is VSSA. Pin DIAG should not be connected to an external pull-up.
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
6 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
VSSA + 8 V
Ch1 mean 5.03 V
VSSA + 2 V VSSA
M 20.0 ms A Ch1 ~ 1.28 V
001aad838
Fig 5. Pin DIAG with activated current limiting
input voltage 2
current in the 3 short-circuit (between the speaker terminals)
PWM output 1
pin DIAG 4 Ch1 Ch3 50.0 V 5.00 V 50 ms Ch2 500 mV Ch4 10.0 V 50 ms M 25.0 ms Ch3 1.80 V
50 ms
001aah365
Fig 6. Restart of the TDF8591TH
When the loudspeaker terminals are short-circuited and the OCP is triggered the TDF8591TH is switched off completely and will try to restart every 100 ms (see Figure 6):
* 50 ms after switch off pin DIAG will be released * 100 ms after switch off the amplifier will return to mute * 150 ms after switch off the amplifier will return to operation. If the short-circuit
condition is still present after this time this cycle will be repeated. The average dissipation will be low because of the small duty cycle A short-circuit of the loudspeaker terminals to one of the supply lines will also trigger the activation of the OCP and the amplifier will shut down. During restart the window protection will be activated. As a result the amplifier will not start up after 100 ms and pin DIAG will remain LOW until the short-circuit to the supply lines is removed.
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
7 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
6.4.4 Window protection
The WP checks the conditions at the output pins of the power stage and is activated:
* During the start-up sequence, when pin MODE is switched from standby to mute. In
the event of a short-circuit at one of the output pins to VDD or VSS the start-up procedure is interrupted and the TDF8591TH waits until the short-circuit to the supply lines has been removed. Because the test is done before enabling the power stages, no large currents will flow in the event of a short-circuit.
* When the amplifier is completely shut down due to activation of the OCP by a
short-circuit to one of the supply lines, the window protection will then be activated during restart (after 100 ms). As a result the amplifier will not start up until the short-circuit to the supply lines is removed.
6.4.5 Supply voltage protections
If the supply voltage drops below 12.5 V, the UVP circuit is activated and the TDF8591TH switch-off will be silent and without pop noise. When the supply voltage rises above 12.5 V, the TDF8591TH is restarted again after 100 ms. If the supply voltage exceeds 33 V the OVP circuit is activated and the power stages will shut down. It is re-enabled as soon as the supply voltage drops below 33 V. So in this case no timer of 100 ms is started. The maximum operating supply voltage is 29 V and if the supply voltage is above the maximal allowable voltage of 34 V (see Section 7), the TDF8591TH can be damaged, irrespective of an activated OVP. See Section 12.6 "Pumping effects" for more information about the use of the OVP. An additional UBP circuit compares the positive analog (VDDA) and the negative analog (VSSA) supply voltages and is triggered if the voltage difference between them exceeds the unbalance threshold level, which is expressed as follows: V th ( unb ) 0.15 x ( V DDA - V SSA ) V When the supply voltage difference VDDA - VSSA exceeds Vth(unb), the TDF8591TH switches off and is restarted again after 100 ms. Example: With a symmetrical supply of VDDA = 20 V and VSSA = -20 V, the unbalance protection circuit will be triggered if the unbalance exceeds approximately 6 V. In Table 4 an overview is given of all protections and the effect on the output signal.
Table 4. TF OTP OCP WP UVP OVP UBP
[1] [2]
TDF8591TH_1
Overview protections TDF8591TH Restart every 100 ms N N[2] N[3] N Y N Y DIAG N N Y Y N N N N Y N[3] Y[4] Y Y Y Y[1] Y[2] Y[3] Y N Y N
Protection name Complete shut down Restart directly
Amplifier gain will depend on junction temperature and heat sink size. Thermal foldback will influence restart timing depending on heat sink size.
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
8 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
[3] [4]
Only complete shut down of amplifier in case of a short-circuit. In all other cases current limiting resulting in clipping output signal. Fault condition detected during (every) transition between standby-to-mute and during restart after activation of OCP (short-circuit to one of the supply lines).
6.5 Diagnostic output
Pin DIAG is pulled LOW when the OCP is triggered. With a continuous short-circuited load a switching pattern in the voltage on pin DIAG is observed (see Figure 6). A permanent LOW on pin DIAG indicates a short-circuit to the supply lines whereas a short-circuited load causes a switching DIAG pin (see Section 6.4.3). The pin DIAG reference voltage is VSSA. Pin DIAG should not be connected to an external pull-up. An example of a circuit to read out and level shift the diagnostic data is given in Figure 7. V5V represents a logic supply that is used in the application by the microprocessor that reads out the DIAG data.
VDDA
5.6 V 100 k
V5V
10 k
DIAG out
M2
100 k
DIAG
M1
SGND
27 k
VSSA
001aad840
Fig 7. DIAG readout circuit with level shift
6.6 Differential inputs
For a high Common Mode Rejection Ratio (CMRR) and a maximum of flexibility in the application, the audio inputs are fully differential. By connecting the inputs anti-parallel the phase of one of the channels can be inverted, so that a load can be connected between the two output filters. In this case the system operates as a mono BTL amplifier. The input configuration for a mono BTL application is illustrated in Figure 8. In the stereo SE configuration it is also recommended to connect the two differential inputs in anti-phase. This has advantages for the current handling of the supply voltage at low signal frequencies (supply pumping).
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
9 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
IN1P IN1M
SGND
IN2P IN2M
001aad841
Input resistors are referred to SGND.
a. Internal circuitry
IN1P IN1M Vin IN2P IN2M
OUT1
SGND
OUT2
power stage
mbl466
b. External connections Fig 8. Input configuration for mono BTL application
7. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions VDDP1 and VDDA1 referred to SGND1; VDDP2 and VDDA2 referred to SGND2 VSSP1 and VSSA1 referred to SGND1; VSSP2 and VSSA2 referred to SGND2 Min -0.3 Max +34 Unit V
VSS
negative supply voltage
-34
+0.3
V
VP IOSM Tstg Tamb Tj VBOOT1 VBOOT2 VSTABI
TDF8591TH_1
supply voltage non-repetitive peak output current storage temperature ambient temperature junction temperature voltage on pin BOOT1 voltage on pin BOOT2 voltage on pin STABI referred to OUT1 referred to OUT2 referred to VSSD
[1] [1] [2]
-0.3 -55 -40 -40 0 0 -
+66 12 +150 +85 +150 14 14 14
V A C C C V V V
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
10 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
Table 5. Limiting values ...continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VMODE VOSC VIN1M VIN1P VIN2M VIN2P VDIAG VO
[1] [2] [3]
Conditions referred to SGND2 referred to VSSD referred to SGND1 referred to SGND1 referred to SGND2 referred to SGND2 referred to VSSD
[3]
Min 0 0 -5 -5 -5 -5 0 VSSP - 0.3
Max 8 40 +5 +5 +5 +5 9
Unit V V V V V V V
voltage on pin MODE voltage on pin OSC voltage on pin IN1M voltage on pin IN1P voltage on pin IN2M voltage on pin IN2P voltage on pin DIAG output voltage
VDDP + 0.3 V
Pin BOOT should not be loaded by any other means than the boot capacitor. A short-circuit between pin BOOT and VSS will damage the device. Pin STABI should not be loaded by an external circuit. A short-circuit between pin STABI and a voltage source or VSS will damage the device. Pin DIAG should not be connected to a voltage source or to a pull-up resistor. An example of a circuit that can be used to read out diagnostic data is given in Figure 7.
8. Thermal characteristics
Table 6. Symbol Rth(j-c) Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to case thermal resistance from junction to ambient In free air Conditions Typ 1 35 Unit K/W K/W
9. Static characteristics
Table 7. Static characteristics VP = 27 V; fosc = 310 kHz; Tamb = -40 C to +85 C; Tj = -40 C to +150 C; unless otherwise specified. Symbol Supply VP Iq(tot) Istb IMODE VMODE supply voltage total quiescent current standby current current on pin MODE voltage on pin MODE no load, no filter, no snubber network connected Tj = -40 C to +85 C VMODE = 5.5 V Standby mode Mute mode Operating mode Diagnostic output; pin DIAG (reference to VSSD) VOL VOH VI
TDF8591TH_1
Parameter
Conditions
[1]
Min 14 [2][3] [2][3] [2][3]
Typ 27 50 150 100 8.4 0
Max 29 65 500 300 0.8 2.8 6 0.8 9 -
Unit V mA A A V V V V V V
11 of 34
Mode select input; pin MODE (reference to SGND2) 0 2.2 4.2 -
LOW-level output voltage HIGH-level output voltage input voltage
activated OCP or WP no activated OCP or WP
[4] [4]
Audio inputs; pins IN1M, IN1P (reference to SGND1), IN2P and IN2M (reference to SGND2)
[2]
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
Table 7. Static characteristics ...continued VP = 27 V; fosc = 310 kHz; Tamb = -40 C to +85 C; Tj = -40 C to +150 C; unless otherwise specified. Symbol VO(offset) Parameter output offset voltage Conditions SE; mute SE; operating BTL; mute BTL; operating Stabilizer output; pin STABI (reference to VSSP1) VO output voltage mute and operating; with respect to VSSD 11 12.5 14 V
[5] [5]
Min -
Typ -
Max 20 170 30 240
Unit mV mV mV mV
Amplifier outputs; pins OUT1 and OUT2
Temperature protection Tprot Tact(th_fold) protection temperature thermal foldback activation temperature closed loop SE voltage gain reduced with 6 dB
[6]
145
160 150
180 -
C C
[1] [2] [3] [4] [5] [6]
The circuit is DC adjusted at VP = 12.5 V to 30 V. Refers to usage in a symmetrical supply application (see Section 12.7). In an asymmetrical supply application the SGND voltage should be defined by an external circuit. The transition between Standby and Mute mode contains hysteresis, while the slope of the transition between Mute and Operating mode is determined by the time constant on pin MODE (see Figure 9). Pin DIAG should not be connected to an external pull-up. DC output offset voltage is applied to the output during the transition between Mute and Operating mode in a gradual way. The dVO(offset)/dt caused by any DC output offset is determined by the time constant on pin MODE. At a junction temperature of approximately Tact(th_fold) - 5 C the gain reduction will commence and at a junction temperature of approximately Tact(th_fold) + 5 C the amplifier mutes.
VO(offset)
slope is directly related to the time constant on pin MODE
operating STBY MUTE ON
mute
0
0.8
2.2
2.8
5.5 4.2 VMODE (V)
001aad842
Fig 9. Behavior of pin MODE
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
12 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
10. Dynamic characteristics
10.1 Dynamic characteristics (SE)
Table 8. Dynamic characteristics (SE) VP = 27 V; RL = 4 ; fi = 1 kHz; fosc = 310 kHz; Rs(L) < 0.1 [1]; Tamb = -40 C to +85 C; Tj = -40 C to +150 C; unless otherwise specified. See Section 12.7 for the SE application schematics. The 2nd-order demodulation filter coil is referred to as L and the capacitor as C. Symbol Po Parameter output power Conditions L = 10 H; C = 1 F; Tj = 85 C; RL = 2 ; VP = 28 V; THD = 0.5 % L = 10 H; C = 1 F; Tj = 85 C; RL = 2 ; VP = 28 V; THD = 10 % L = 22 H; C = 680 nF; Tj = 85 C; RL = 4 ; VP = 29 V; THD = 0.5 % L = 22 H; C = 680 nF; Tj = 85 C; RL = 4 ; VP = 29 V; THD = 10 % IOM THD Gv(cl) SVRR peak output current current limiting, see Section 6.4.3
[3] [3] [2]
Min 12 25 40 45
[5] [5] [6] [6]
Typ 130 158 82 100 0.02 0.10 26 55 50 55 80 68 170 145 125 85 70 73 75
Max 0.2 27 1 -
Unit W W W W A % % dB dB dB dB dB k V V V V dB dB dB dB
[2]
[2]
[2]
total harmonic distortion Po = 1 W; fi = 1 kHz Po = 1 W; fi = 10 kHz closed-loop voltage gain supply voltage ripple rejection operating; fripple = 100 Hz operating; fripple = 1 kHz mute; fripple = 1 kHz standby; fripple = 100 Hz
[4] [4] [4] [4]
|Zi(dif)| Vn(o)
differential input impedance noise output voltage
between the input pins INxP and INxM operating; VP = 27 V; RS = 0 operating; VP = 18 V; RS = 0 mute; VP = 27 V mute; VP = 18 V
-
cs |Gv| mute CMRR
channel separation voltage gain difference mute attenuation
Po = 1 W; RS = 0 ; fi = 1 kHz fi = 1 kHz; Vi = 1 V (RMS value)
[7]
common mode rejection fi(CM) = 1 kHz; Vi(CM) = 1 V (RMS value) ratio
-
[1] [2] [3] [4] [5] [6] [7]
Rs(L) is the series resistance of inductor of low-pass LC filter in the application. Output power is measured indirectly; based on RDSon measurement (see Section 12.2). THD is measured in a bandwidth of 22 Hz to 20 kHz, AES brick wall. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (peak-to-peak value); source resistance RS = 0 . B = 22 Hz to 20 kHz, AES brick wall (see Section 12.4). B = 22 Hz to 20 kHz, AES brick wall, independent of RS (see Section 12.4). Vi(CM) is the input common mode voltage.
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
13 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
10.2 Dynamic characteristics (BTL)
Table 9. Dynamic characteristics (BTL) VP = 27 V; RL = 8 ; fi = 1 kHz; fosc = 310 kHz; Rs(L) < 0.1 [1]; Tamb = -40 C to +85 C; Tj = -40 C to +150 C; unless otherwise specified. See Section 12.7 for the BTL application schematics. The 2nd order demodulation filter coil is referred to as L and the capacitor as C. Symbol Po Parameter output power Conditions L = 10 H, C = 1 F; Tj = 85 C; RL = 4 ; VP = 18 V; THD = 0.5 % L = 10 H; C = 1 F; Tj = 85 C; RL = 4 ; VP = 18 V; THD = 10 % L = 22 H; C = 680 nF; Tj = 85 C; RL = 4 ; VP = 27 V; THD = 0.5 % L = 22 H; C = 680 nF; Tj = 85 C; RL = 4 ; VP = 27 V; THD = 10 % IOM THD Gv(cl) SVRR peak output current current limiting, see Section 6.4.3
[3] [3] [2]
Min 12 31 50 22
[5] [5] [6] [6]
Typ 110 139 250 310 0.02 0.15 32 68 68 68 80 34 240 200 180 125 70 75
Max 0.2 33 -
Unit W W W W A % % dB dB dB dB dB k V V V V dB dB
[2]
[2]
[2]
total harmonic distortion Po = 1 W; fi = 1 kHz Po = 1 W; fi = 10 kHz closed-loop voltage gain supply voltage ripple rejection operating; fripple = 100 Hz operating; fripple = 1 kHz mute; fripple = 1 kHz standby; fripple = 100 Hz
[4] [4] [4] [4]
|Zi(dif)| Vn(o)
differential input impedance noise output voltage
measured between the input pins INxP and INxM operating; VP = 27 V; RS = 0 operating; VP = 18 V; RS = 0 mute; VP = 27 V mute; VP = 18 V
-
mute CMRR
mute attenuation
fi = 1 kHz; Vi = 1 V (RMS value)
common mode rejection fi(CM) = 1 kHz; Vi(CM) = 1 V (RMS value) ratio
[1] [2] [3] [4] [5] [6]
Rs(L) is the series resistance of inductor of low-pass LC filter in the application. Output power is measured indirectly; based on RDSon measurement (see Section 12.2). THD is measured in a bandwidth of 22 Hz to 20 kHz, AES brick wall. Maximum limit is guaranteed but may not be 100 % tested. Vripple = Vripple(max) = 2 V (peak-to-peak value); RS = 0 . B = 22 Hz to 20 kHz, AES brick wall (see Section 12.4). B = 22 Hz to 20 kHz, AES brick wall, independent on RS (see Section 12.4).
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
14 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
11. Switching characteristics
Table 10. Switching characteristics VDD = 27 V; Tamb = -40 C to +85 C; Tj = -40 C to +150 C; unless otherwise specified. Symbol fosc Parameter oscillator frequency Conditions typical; Rext(OSC) = 30.0 k maximum; Rext(OSC) = 15.4 k minimum; Rext(OSC) = 48.9 k External oscillator or frequency tracking VH(OSC)min minimum HIGH-level voltage on pin OSC VL(OSC)max maximum LOW-level voltage on pin OSC ftrack RDSon(ls) RDSon(hs) tracking frequency range low-side drain-source on-state resistance high-side drain-source on-state resistance Tj = 85 C; IDS = 6 A Tj = 25 C; IDS = 6 A Tj = 85 C; IDS = 6 A Tj = 25 C; IDS = 6 A referred to SGND referred to SGND 4 0 210 185 140 220 160 6 1 600 205 155 245 175 V V kHz m m m m Min 290 Typ 310 560 200 Max 344 Unit kHz kHz kHz Internal oscillator
Drain source on-state resistance of the output transistors
12. Application information
12.1 BTL application
When using the power amplifier in a mono BTL application the inputs of both channels must be connected in parallel and the phase of one of the inputs must be inverted (see Figure 8). The loudspeaker is connected between the outputs of the two single-ended demodulation filters.
12.2 Output power estimation
The achievable output powers in SE and BTL applications can be estimated using the following expressions: RL f osc 2 ------------------------------------------------------ x V x 1 - t P w ( min ) x --------- R L + R DSon ( hs ) + R s ( L ) 2 = --------------------------------------------------------------------------------------------------------------------------------- W 2 x RL RL f osc 2 ------------------------------------------------------------------------------------------- x 2V x 1 - t P w ( min ) x --------- R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L ) 2 = -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- W 2 x RL
SE: P o ( 0.5% )
BTL: P o ( 0.5% )
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
15 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
Peak output current, internally limited to 12 A: f osc V P x 1 - t w ( min ) x --------- 2 = ------------------------------------------------------------ A R L + R DSon ( hs ) + R s ( L ) f osc 2V P x 1 - t w ( min ) x -------- 2 = ------------------------------------------------------------------------------------------- A R L + ( R DSon ( hs ) + R DSon ( ls ) ) + 2R s ( L )
SE: I OM
BTL: I OM Variables:
RL = load resistance Rs(L) = series resistance of the filter coil RDSon(hs) = high side drain source on-state resistance (temperature dependent) RDSon(ls) = low side drain source on-state resistance (temperature dependent) fosc = oscillator frequency tw(min) = minimum pulse width (typical 150 ns, temperature dependent) VP = single sided supply voltage [or 0.5 (VDD + |VSS|)] Po(0.5%) = output power at the onset of clipping IOM should be below 12 A (see Section 6.4.3). IOM is the sum of the current through the load and the ripple current. The value of the ripple current is dependent on the coil inductance and voltage drop over the coil.
12.3 External clock
If two or more class-D amplifiers are used it is recommended that all devices run at the same switching frequency. This can be realized by connecting all OSC pins together and feed them from an external oscillator. The internal oscillator requires an external Rext(OSC) and Cext(OSC) between pins OSC and VSSA. For application of an external oscillator it is necessary to force OSC to a DC level above SGND. The internal oscillator is disabled and the PWM modulator will switch with the external frequency. The duty cycle of the external clock should be between 47.5 % and 52.5 %. The noise contribution of the internal oscillator is supply voltage dependent. In low noise applications running at high supply voltage an external low noise oscillator is recommended.
12.4 Noise
Noise should be measured using a high-order low-pass filter with a cut-off frequency of 20 kHz. The standard audio band pass filters used in audio analyzers do not suppress the residue of the carrier frequency sufficiently to ensure a reliable measurement of the audible noise. Noise measurements should preferably be carried out using AES 17 (Brick Wall) filters or the Audio Precision AUX 0025 filter, which was designed especially for measuring switching (class-D) amplifiers.
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
16 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
12.5 Heat sink requirements
In some applications it may be necessary to connect an external heat sink to the TDF8591TH. The thermal foldback activates on Tj = 140 C. The expression below shows the relationship between the maximum power dissipation before activation of the thermal foldback and the total thermal resistance from junction to ambient: T j - T amb R th ( j -a ) = ----------------------- P The power dissipation (P) is determined by the efficiency () of the TDF8591TH. The efficiency measured as a function of output power is given in Figure 30 and 31. The power dissipation can be derived as function of output power (see Figure 32 and 33). Example of a heatsink calculation for the 4 BTL application with 18 V supply:
* An audio signal with a crest factor of 10 (the ratio between peak power and average
power is 10 dB), this means that the average output power is 110 of the peak power The peak RMS output power level is 110 W (0.5 % THD level) The average power is 0.1 x 110 W = 11 W The dissipated power at an output power of 11 W is approximately 5 W The total Rth(j-a) = (140 - 85) / 5 = 11 K/W, if the maximum expected Tamb = 85 C The total thermal resistance Rth(j-a) = Rth(j-c) + Rth(c-h) + Rth(h-a) Rth(j-c) = 1 K/W, Rth(c-h) = 0.5 K/W to 1 K/W (dependent on mounting), so Rth(h-a) would then be: 11 - (1 + 1) = 9 K/W
* * * * * *
12.6 Pumping effects
When the TDF8591TH is used in a SE configuration, a so-called pumping effect can occur. During one switching interval, energy is taken from one supply (e.g. VDDA1), while a part of that energy is delivered back to the other supply line (e.g. VSSA1) and visa versa. When the voltage supply source cannot sink energy, the voltage across the output capacitors of that voltage supply source will increase: the supply voltage is pumped to higher levels. The voltage increase caused by the pumping effect depends on:
* * * * *
Speaker impedance Supply voltage Audio signal frequency Value of decoupling capacitors on supply lines Source and sink currents of other channels
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
17 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
The pumping effect should not cause a malfunction of either the audio amplifier and/or the voltage supply source. For instance, this malfunction can be caused by triggering of the UVP, OVP or UBP of the amplifier. Best remedy for pumping effects is to use the TDF8591TH in a mono full-bridge application. In case of dual half-bridge application adapt the supply voltage (e.g. increase supply decoupling capacitors).
12.7 Application schematics
For SE application (see Figure 10):
* A solid ground plane around the TDF8591TH is necessary to prevent emission * 100 nF Surface Mounted Device (SMD) capacitors must be placed as close as
possible to the supply voltage pins of the TDF8591TH
* The heatsink of the HSOP24 package of the TDF8591TH is connected to pin VSSD * The external heatsink must be connected to the ground plane * Use a thermal conductive, electrically isolating Sil-Pad between the backside of the
TDF8591TH and the external heatsink For BTL application (see Figure 11):
* A solid ground plane around the TDF8591TH is necessary to prevent emission * 100 nF SMD capacitors must be placed as close as possible to the supply voltage
pins of the TDF8591TH
* The heatsink of the HSOP24 package of the TDF8591TH is connected to pin VSSD * The external heatsink must be connected to the ground plane * Use a thermal conductive, electrically isolating Sil-Pad between the backside of the
TDF8591TH and the external heatsink
* The differential inputs enable the best system level audio performance with
unbalanced signal sources. In case of hum due to floating inputs connect the shielding or source ground to the amplifier ground
* Minimum total required capacity per supply voltage line is 3300 F
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
18 of 34
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Product data sheet Rev. 01 -- 5 March 2008
(c) NXP B.V. 2008. All rights reserved. TDF8591TH_1
NXP Semiconductors
R2 L1 BEAD 10
VDDP VDDA VDDP
R1 5.6 k R3 5.6 k DZ1 5V6 S1 R4 5.6 k S2 C4 100 F (10 V)
CON1 +25 V VDD 1 GND 2 3 -25 V VSS
C1 100 nF
C2 47 F (35 V)
C3 470 F (35 V)
C7 100 nF
C5 47 F (35 V) L2 BEAD
C6 470 F (35 V)
VSSP
R5 10
ON/OFF VSSA
OPERATE/MUTE VDDP
C8
VSSA
VSSP
VDDA
VSSA
C9 100 nF
R6 30 k C14
47 F (63 V) C15 100 nF C16 100 nF
C12
C13
VDDP
C10 220 pF
VSSP
C11 220 pF
FB GND
100 nF 100 nF
FB GND
100 nF
SINGLE-ENDED OUTPUT FILTER VALUES LS1/LS2 L3/L4 C22/C31 2 4 6 8 10 H 22 H 33 H 47 H 1 F 680 nF 470 nF 330 nF
MODE
VDDA1
VDDP1
VSSA1
VSSP1
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
IN1
C17 1 nF
OSC
R8 5.6 k R10
C18 470 nF C20 470 nF C19 220 pF
IN1P 10 8
12
7
6
14
17 16 OUT1 BOOT1 C21
15 nF
R7 10
L3
OUT1P LS1
R9 22 C22 C24 100 nF
IN1M SGND1
9 11
OUT1M
C23 1 nF C25 1 nF
5.6 k
15
FB GND SGND2
R11 5.6 k C26 470 nF C29 470 nF C28 220 pF
TDF8591TH
2 5 21 OUT2
R13 10
IN2P
22
BOOT2 C27
15 nF
FB GND
L4
OUT2M LS2
R14 22 C31 C32 100 nF
IN2
C30 1 nF
R12 5.6 k
IN2M
4 3 VDDA2 1 VSSA2 13 DIAG 19 n.c. 24 VSSD 18 STABI 23 VDDP2 20 VSSP2
C40 220 pF
OUT2P
TDF8591TH
C34
C35 100 nF
FB GND
100 nF
FB GND
C33 47 pF C36 100 nF
C37 100 nF
C38 100 nF
C39 100 nF
C41 220 pF
FB GND
VDDA
VSSA
VSSA
VSSP
VDDP
VSSP
VDDP
VSSP
001aah232
19 of 34
Fig 10. SE application schematic
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Product data sheet Rev. 01 -- 5 March 2008
(c) NXP B.V. 2008. All rights reserved. TDF8591TH_1
NXP Semiconductors
R2 L1 BEAD 10
VDDP VDDA VDDP
R1 5.6 k R3 5.6 k DZ1 5V6 S1 R4 5.6 k S2 C4 100 F (10 V)
CON1 +25 V VDD 1 GND 2 3 -25 V VSS
C1 100 nF
C2 47 F (35 V)
C3 470 F (35 V)
C7 100 nF
C5 47 F (35 V) L2 BEAD
C6 470 F (35 V)
VSSP
R5 10
ON/OFF VSSA
OPERATE/MUTE VDDP
C8
VSSA
VSSP
VDDA
VSSA
C9 100 nF
R6 30 k C14
47 F (63 V) C15 100 nF C16 100 nF
C12
C13
VDDP
C10 220 pF
VSSP
C11 220 pF
FB GND
100 nF 100 nF
FB GND
100 nF
BRIDGE-TIED LOAD OUTPUT FILTER VALUES LOAD L C 4 8 10 H 22 H 1 F 680 nF
MODE
VDDA1
VDDP1
VSSA1
VSSP1
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
IN1
R8 5.6 k R10 5.6 k J1
C23 1 nF C18 1 F C20 1 F C25 1 nF
OSC
IN1P 10 8
C19 220 pF
12
7
6
14
17 16 OUT1 BOOT1 C21
15 nF
R7 10 L3
OUT1P LS1
R9 22 C22 C24 100 nF
IN1M SGND1
9 11
OUT2M
15
SGND2 FB GND IN2P
C28 220 pF
TDF8591TH
2 5 21 4 3 VDDA2 1 VSSA2 13 DIAG 19 n.c. 24 VSSD 18 STABI 23 VDDP2 20 VSSP2
C31 C40 220 pF C41 220 pF
22
BOOT2 C27
15 nF
FB GND
L4
OUT2
R13 10
IN2M
R14 22 C32 100 nF
TDF8591TH
C34
C35 100 nF
FB GND
100 nF
FB GND
C33 47 pF C36 100 nF
C37 100 nF
C38 100 nF
C39 100 nF
FB GND
VDDA
VSSA
VSSA
VSSP
VDDP
VSSP
VDDP
VSSP
001aah233
20 of 34
Fig 11. BTL application schematic
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
12.8 Application graphs
102 THD (%) 10
001aah197
102 THD (%) 10
001aah196
1
(1)
1
(1)
10-1
(2)
10-1
(2)
10-2
(3)
10-2
(3)
10-3 10-1
1
10
102 Po (W)
103
10-3 10-1
1
10
102 Po (W)
103
VP = 27 V; double coils; C = 680 nF. (1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 Hz.
VP = 27 V; double coils; C = 680 nF. (1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 Hz.
a. RL = 4 .
b. RL = 2 .
Fig 12. Total harmonic distortion as a function of output power, SE application
102 THD (%) 10
001aah199
102 THD (%) 10
001aah198
1
(1)
1
10-1
(2)
10-1
(1) (2)
10-2
(3)
10-2
(3)
10-3 10-1
1
10
102 Po (W)
103
10-3 10-1
1
10
102 Po (W)
103
VP = 27 V; double coils; C = 680 nF. (1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 Hz.
VP = 27 V; double coils; C = 680 nF. (1) f = 10 kHz. (2) f = 1 kHz. (3) f = 100 Hz.
a. RL = 8
b. RL = 4
Fig 13. Total harmonic distortion as a function of output power, BTL application
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
21 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
1 THD (%) 10-1
(1) (2) (3) (4)
001aah200
1 THD (%) 10-1
001aah201
(1) (2) (3) (4)
10-2
10-2
10-3 10-2
10-1
1
10 f (kHz)
102
10-3 10-2
10-1
1
10 f (kHz)
102
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 18 V. (3) VP = 27 V. (4) VP = 29 V.
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 18 V. (3) VP = 27 V. (4) VP = 29 V.
Fig 14. Total harmonic distortion as a function of frequency, SE application with 2 load
Fig 15. Total harmonic distortion as a function of frequency, SE application with 4 load
1 THD (%) 10-1
(1) (2) (3) (4)
001aah202
10-2
10-3 10-2
10-1
1
10 f (kHz)
102
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 29 V. (3) VP = 18 V. (4) VP = 27 V.
Fig 16. Total harmonic distortion as a function of frequency, SE application with 8 load
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
22 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
1 THD (%) 10-1
(1) (2) (3) (4)
001aah203
1 THD (%) 10-1
001aah204
(1) (2) (3) (4)
10-2
10-2
10-3 10-2
10-1
1
10 f (kHz)
102
10-3 10-2
10-1
1
10 f (kHz)
102
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 18 V. (3) VP = 27 V. (4) VP = 29 V.
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 18 V. (3) VP = 27 V. (4) VP = 29 V.
Fig 17. Total harmonic distortion as a function of frequency, BTL application with 2 load
Fig 18. Total harmonic distortion as a function of frequency, BTL application with 4 load
1 THD (%) 10-1
(1) (2) (3) (4)
001aah205
10-2
10-3 10-2
10-1
1
10 f (kHz)
102
Po = 1 W; C = 680 nF; L = 22 H. (1) VP = 14 V. (2) VP = 18 V. (3) VP = 27 V. (4) VP = 29 V.
Fig 19. Total harmonic distortion as a function of frequency, BTL application with 8 load
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
23 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
100 cs (dB) 80
(1) (2) (3)
001aah206
100 cs (dB) 80
001aah207
60
60
(1) (2)
(3)
40
40
20
20
0 10-2
10-1
1
10 f (kHz)
102
0 10-2
10-1
1
10 f (kHz)
102
RL = 4 . (1) VP = 29 V. (2) VP = 27 V. (3) VP = 14 V.
RL = 4 . (1) VP = 27 V. (2) VP = 29 V. (3) VP = 14 V.
a. Channel 2 to channel 1.
b. Channel 1 to channel 2.
Fig 20. Channel separation as a function of frequency, SE application
100 CMRR (dB)
001aah208
100 CMRR (dB)
(1) (2) (3)
001aah209
(1) (2)
60
60
20 10-2
10-1
1
10 f (kHz)
102
20 10-2
10-1
1
10 f (kHz)
102
(1) VP = 29 V. (2) VP = 27 V. (3) VP = 14 V.
(1) VP = 14 V. (2) VP = 29 V. (3) VP = 27 V.
a. Channel 1.
b. Channel 2.
Fig 21. Common mode rejection ratio as a function of frequency, SE application
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
24 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
100 CMRR (dB)
001aah210
(1) (2)
60
20 10-2
10-1
1
10 f (kHz)
102
(1) VP = 14 V. (2) VP = 27 V and 29 V.
Fig 22. Common mode rejection ratio as a function of frequency; BTL application
120 SVRR (dB) 100
(1) (2) (3) (4)
001aah211
120 SVRR (dB) 100
(1) (2) (3) (4)
001aah212
80
80
60 10-2
10-1
1
10 f (kHz)
102
60 10-2
10-1
1
10 f (kHz)
102
(1) ripple in antiphase. (2) ripple on VDD only. (3) ripple on VSS only. (4) ripple in phase.
(1) ripple on VSS only. (2) ripple on VDD only. (3) ripple in phase. (4) ripple in antiphase.
a. SE application; RL = 4
b. BTL application; RL = 8
Fig 23. Supply voltage ripple rejection as a function of frequency; Standby mode
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
25 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
80 SVRR (dB) 60
(1) (2) (3) (4)
001aah213
80 SVRR (dB) 60
(1) (2) (3) (4)
001aah214
40
40 20
0 10-2
10-1
1
10 f (kHz)
102
20 10-2
10-1
1
10 f (kHz)
102
(1) ripple on VDD only. (2) ripple in antiphase. (3) ripple on VSS only. (4) ripple in phase.
(1) ripple on VSS only. (2) ripple on VDD only. (3) ripple in antiphase. (4) ripple in phase.
a. SE application; RL = 4
b. BTL application; RL = 8
Fig 24. Supply voltage ripple rejection as a function of frequency; Mute mode
80 SVRR (dB) 60
(1) (2) (3) (4)
001aah215
80 SVRR (dB) 60
001aah216
40
(1)
40 20
(2) (3) (4)
0 10-2
10-1
1
10 f (kHz)
102
20 10-2
10-1
1
10 f (kHz)
102
(1) ripple on VDD only. (2) ripple in antiphase. (3) ripple on VSS only. (4) ripple in phase.
(1) ripple in phase. (2) ripple on VSS only. (3) ripple on VDD only. (4) ripple in antiphase.
a. SE application; RL = 4
b. BTL application; RL = 8
Fig 25. Supply voltage ripple rejection as a function of frequency; Operating mode
TDF8591TH_1
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Product data sheet
Rev. 01 -- 5 March 2008
26 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
100 mute (dB) 80
(1) (2) (3)
001aah217
100 mute (dB) 80
(1) (2) (3)
001aah218
60
60
40
40
20
20
0 10-2
10-1
1
10 f (kHz)
102
0 10-2
10-1
1
10 f (kHz)
102
(1) VP = 14 V. (2) VP = 27 V. (3) VP = 29 V.
(1) VP = 14 V. (2) VP = 27 V. (3) VP = 29 V.
a. Channel 1
b. Channel 2
Fig 26. Mute attenuation as a function of frequency, SE application
100 mute (dB) 80
001aah219
(1) (2) (3)
60
40
20
0 10-2
10-1
1
10 f (kHz)
102
(1) VP = 14 V. (2) VP = 27 V. (3) VP = 29 V.
Fig 27. Mute attenuation as a function of frequency, BTL application
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
27 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
200 Po (W) 160
(1)
001aah220
120 Po (W) 80
001aah221
(1)
(2)
(2)
120
80 40 40
0 25 35 45 55 VP (V) 65
0 20 30 40 50 60 VP (V) 70
f = 1 kHz; double coils; C = 680 nF. (1) THD = 10 %. (2) THD = 0.5 %.
f = 1 kHz; double coils; C = 680 nF. (1) THD = 10 %. (2) THD = 0.5 %.
a. RL = 2
b. RL = 4
Fig 28. Output power as a function of supply voltage, SE application
400 Po (W) 300
(2)
001aah222
260 Po (W)
(1)
001aah223
(1)
180
(2)
200
100 100
0 20 30 40 50 60 VP (V) 70
20 20 30 40 50 60 VP (V) 70
f = 1 kHz; double coils; C = 680 nF. (1) THD = 10 %. (2) THD = 0.5 %.
f = 1 kHz; double coils; C = 680 nF. (1) THD = 10 %. (2) THD = 0.5 %.
a. RL = 4
b. RL = 8
Fig 29. Output power as a function of supply voltage, BTL application
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
28 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
100 (%) 80
001aah224
100 (%) 80
001aah225
60
60
40
40
20
20
0 0 40 80 120 160 200 Po (W)
0 0 40 80 Po (W) 120
a. RL = 2 ; VP = 28 V.
b. RL = 4 ; VP = 29 V
Fig 30. Efficiency as a function of output power (one channel), SE application
100 (%) 80
001aah226
100 (%) 80
001aah227
60
60
40
40
20
20
0 0 50 100 Po (W) 150
0 0 50 100 Po (W) 150
a. RL = 4 ; VP = 18 V.
b. RL = 4 ; VP = 27 V
Fig 31. Efficiency as a function of output power, BTL application
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
29 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
40 P (W) 30
001aah228
12 P (W) 8
001aah229
20
4 10
0 0 40 80 120 160 200 Po (W)
0 0 20 40 60 80 100 Po (W)
a. RL = 2 ; VP = 28 V.
b. RL = 4 ; VP = 29 V
Fig 32. Power dissipation as a function of output power (one channel), SE application
16 P (W) 12
001aah230
20 P (W) 16
001aah231
12 8 8
4 4
0 0 40 80 120 Po (W) 160
0 0 40 80 120 Po (W) 160
a. RL = 4 ; VP = 18 V.
b. RL = 4 ; VP = 27 V
Fig 33. Power dissipation as a function of output power, BTL application
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Stress test qualification for integrated circuits, and is suitable for use in automotive applications.
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
30 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
14. Package outline
HSOP24: plastic, heatsink small outline package; 24 leads; low stand-off height SOT566-3
E D x
A X
c y E2 HE vM A
D1 D2 1 pin 1 index Q A2 E1 A4 Lp detail X 24 Z e bp 13 wM (A3) A 12
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A A2 max. 3.5 3.5 3.2 A3 0.35 A4(1) bp c D(2) D1 D2 1.1 0.9 E(2) 11.1 10.9 E1 6.2 5.8 E2 2.9 2.5 e 1 HE 14.5 13.9 Lp 1.1 0.8 Q 1.7 1.5 v w x y Z 2.7 2.2 8 0
+0.08 0.53 0.32 16.0 13.0 -0.04 0.40 0.23 15.8 12.6
0.25 0.25 0.03 0.07
Notes 1. Limits per individual lead. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT566-3 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION
ISSUE DATE 03-02-18 03-07-23
Fig 34. Package outline SOT566-3 (HSOP24)
TDF8591TH_1 (c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
31 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
15. Revision history
Table 11. Revision history Release date 20080305 Data sheet status Product data sheet Change notice Supersedes Document ID TDF8591TH_1
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
32 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
TDF8591TH_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 5 March 2008
33 of 34
NXP Semiconductors
TDF8591TH
2 x 100 W SE (4 ) or 1 x 310 W BTL (4 ) class-D amplifier
18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 7 8 9 10 10.1 10.2 11 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 13 13.1 14 15 16 16.1 16.2 16.3 16.4 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pulse width modulation frequency . . . . . . . . . . 5 Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal foldback . . . . . . . . . . . . . . . . . . . . . . . 6 Overtemperature protection . . . . . . . . . . . . . . . 6 Overcurrent protection . . . . . . . . . . . . . . . . . . . 6 Window protection . . . . . . . . . . . . . . . . . . . . . . 8 Supply voltage protections . . . . . . . . . . . . . . . . 8 Diagnostic output . . . . . . . . . . . . . . . . . . . . . . . 9 Differential inputs . . . . . . . . . . . . . . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Thermal characteristics. . . . . . . . . . . . . . . . . . 11 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Dynamic characteristics (SE) . . . . . . . . . . . . . 13 Dynamic characteristics (BTL) . . . . . . . . . . . . 14 Switching characteristics . . . . . . . . . . . . . . . . 15 Application information. . . . . . . . . . . . . . . . . . 15 BTL application . . . . . . . . . . . . . . . . . . . . . . . . 15 Output power estimation. . . . . . . . . . . . . . . . . 15 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 16 Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Heat sink requirements. . . . . . . . . . . . . . . . . . 17 Pumping effects . . . . . . . . . . . . . . . . . . . . . . . 17 Application schematics . . . . . . . . . . . . . . . . . . 18 Application graphs . . . . . . . . . . . . . . . . . . . . . 21 Test information . . . . . . . . . . . . . . . . . . . . . . . . 30 Quality information . . . . . . . . . . . . . . . . . . . . . 30 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 31 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 32 Legal information. . . . . . . . . . . . . . . . . . . . . . . 33 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 33 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Contact information. . . . . . . . . . . . . . . . . . . . . 33 18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 5 March 2008 Document identifier: TDF8591TH_1

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